The invention relates to the field of synchronizing memory access requests in a multi-processor, parallel computing system with weak consistency.
More about memory synchronization in a multiprocessing system with a weak consistency model can be found in IBM® Power ISA™ Version 2.06 Jan. 30, 2009, e.g. at pp. 653-667, 700-703, and 717. This entire document will also be referred to herein as “PowerPC architecture” or “PPC” and is incorporated by reference. Msync is an instruction type defining ordering requirements for the PowerPC weakly consistent memory model. A core executing an msync is expected to have made all its previously issued writes visible to all cores before any further write may be made visible. The msync instruction is a way of imposing strong or sequential consistency into code that would otherwise be running under the weak consistency model. More about the msync instruction can be found in the article: Janice M. Stone, Robert P. Fitzgerald, “Storage in the PowerPC,” IEEE Micro, pp. 50-58, April, 1995.
The invention arose in the context of the IBM® BluGene® system. In prior generations of this system, communication between nodes, including for synchronization purposes, was via broadcast bus. As numbers of nodes have increased with new generations, the demands on the broadcast bus for communication between nodes have become increasingly burdensome.